Deep-submicron scaling required for ULSI systems dominates design considerations in the microelectronics industry. As the gate electrode length is scaled down, the source and drain junctions must be scaled down accordingly, to suppress the so-called short channel effects (SCE) which degrade performance of scale-downed devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth (X.sub.j) and polycrystalline silicon line width are scaled into the deep-submicron range, parasitic series resistances of the source/drain diffusion layers and polysilicon gate electrodes increase. A conventional approach to the increase in parasitic series resistances of the source/drain diffusion layers and the polysilicon gate electrodes involves salicide technology which comprises forming a layer of titanium disilicide (TiSi.sub.2) on the source/drain regions and gate electrode.
Conventional salicide technology employing TiSi.sub.2 for reducing parasitic series resistance has proven problematic, particularly as design rules plunge into the deep-submicron range, e.g., about 0.18 microns and under. For example, in forming a thin TiSi.sub.2 layer, silicide agglomeration occurs during silicide annealing to effect a phase change from the high resistivity C49 form to the low resistivity C54 form. Such agglomeration further increases the sheet resistance of the silicide film. Moreover, the formation of a thick silicide layer causes a high junction leakage current and low reliability, particularly when forming ultra shallow junctions, e.g., at an X.sub.j of less than about 800 .ANG.. The formation of a thick silicicde consumes crystalline silicon from the underlying semiconductor substrate such that the thick silicide layer approaches and even shorts the ultra-shallow junction, thereby generating a high junction leakage current.
Another problem attendant upon conventional TiSi.sub.2 technology is the well-known increase in sheet resistance as the line width narrows. The parasitic series resistances of source/drain regions and gate electrodes are a major cause of device performance degradation and are emerging as one of the severest impediments to device scaling.
In copending application Ser. No. 09/112,156, filed on Jul. 9, 1998, elevated salicide methodology is disclosed wherein crystalline silicon consumption in the substrate and polycrystalline consumption in the gate electrode upon forming metal silicide layers is replenished.
There exists a need for salicide technology which enables a reduction in the parasitic sheet resistance without generating a high leakage current. There exists a particular need for salicide methodology which avoids the generation of a high leakage current in semiconductor devices having a design rule in the deep-submicron range, e.g., a design rule less than about 0.18 microns.